Automated optical inspection of unit specific patterning

ABSTRACT

A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed as a reconstituted wafer. A plurality of unit specific patterns can be formed by forming a unit specific pattern over each of the plurality of semiconductor die, wherein each of the unit specific patterns is customized to fit its respective semiconductor die. A plurality of images can be acquired by acquiring an image for each of the plurality of unit specific patterns. A plurality of unique reference standards can be created by creating a unique reference standard for each of the plurality of unit specific patterns. Defects can be detected in the plurality of unit specific patterns by comparing one of the plurality of unique reference standards to a corresponding one of the plurality of images for each of the plurality of unit specific patterns.

RELATED APPLICATION

This application is a Continuation application of earlier U.S. patentapplication Ser. No. 14/946,464 to Craig Bishop et al. entitled“AUTOMATED OPTICAL INSPECTION OF UNIT SPECIFIC PATTERNING,” filed Nov.19, 2015, now pending, which claims the benefit of U.S. ProvisionalPatent Application No. 62/081,767 entitled “AUTOMATED OPTICAL INSPECTIONOF ADAPTIVE PATTERNING,” filed Nov. 19, 2014, the entirety of thedisclosures of which are hereby incorporated herein by this reference.

TECHNICAL FIELD

This disclosure relates to semiconductor packages including panelizedpackaging and wafer-level-chip-scale-packages (WLCSPs) and automatedoptical or visual inspection of the semiconductor package duringmanufacturing.

BACKGROUND

Conventional automated optical inspection (AOI), such as for packagingof semiconductor devices that includes fixed or constant features anddoes not include unit specific features of unit specific, is known inthe art, and has been conventionally accomplished by comparing areference image or “golden image” with an image captured during visualinspection of the conventional semiconductor device. The golden image isconstructed by combining multiple images of known good parts. Thecombination of multiple images effectively provides an average oridealized part or package that averages out defects, aberrations,variations, or “noise” that is present on even acceptable, functional,or good parts.

An image captured by visual inspection is simply a visual or graphicalrepresentation, like a photograph, that shows a package or packagecomponent as it actually exists or was made, which can differ from itsoriginal design or intended structure. After having both a golden imageand an actual image captured during visual inspection, the image orimages captured of various parts of semiconductor packages are eachcompared, in turn, against the idealized or standardized golden image.In some instances, the comparison is done by subtraction so that thegolden image and the image captured by visual inspection are comparedpixel-by-pixel to produce a resulting image that shows or indicatesdifferences between the golden image and the image captured by visualinspection. Results of the comparison can be processed with thresholdfilters and spatial filters to find defects in the visually inspectedproduct. Defective products can be identified and dealt withaccordingly.

SUMMARY

A need exists for AOI of semiconductor devices comprising unit specificpattering. Accordingly, in one aspect, a method of AOI for a pluralityof unique semiconductor packages can comprise a method of AOI for aplurality of unique semiconductor packages comprising providing aplurality of semiconductor die formed as a reconstituted wafer. Aplurality of unit specific patterns can be formed as a unit specificpattern over each of the plurality of semiconductor die, wherein each ofthe unit specific patterns is customized to fit its respectivesemiconductor die. A plurality of images can be acquired by acquiring animage for each of the plurality of unit specific patterns. A pluralityof unique reference standards can be created by creating a uniquereference standard for each of the plurality of unit specific patterns.Defects can be detected in the plurality of unit specific patterns bycomparing one of the plurality of unique reference standards to acorresponding one of the plurality of images for each of the pluralityof unit specific patterns. The reconstituted wafer can be singulated toform the plurality of unique semiconductor packages.

The method of AOI for a plurality of unique semiconductor packages canfurther comprise pre-processing the plurality of images for each of theplurality of unit specific patterns by converting the plurality ofimages into a plurality of binary images, the plurality of binary imagesindicating conductive paths and non-conductive paths, creating theplurality of unique reference standards as a plurality of net lists ofXY coordinates, and comparing one of the plurality of net lists of XYcoordinates to the corresponding one of the plurality of binary imagesfor each of the plurality of unit specific patterns by mapping the oneof the plurality of net lists of the XY coordinates onto the one of theplurality of binary images for each of the plurality of unit specificpatterns. The method can further comprise finding a path between XYcoordinates of one of the plurality of net lists within the conductivepaths of the binary images using a search algorithm or connectivityalgorithm to validate electrical connectivity. The method can furthercomprise verifying that separate nets of the plurality of net lists arenot connected using a pixel expansion algorithm or fill algorithm.

The method can further comprise providing a plurality of computer-aideddesign (CAD) images comprising a CAD image corresponding to each of theunit specific patterns formed over each of the plurality ofsemiconductor die, and creating the plurality of unique referencestandards by creating a plurality of dynamic reference images byrasterizing or modeling the plurality of CAD images for each of theplurality of unit specific patterns. The method can further compriserasterizing the plurality of CAD images for each of the plurality ofunit specific patterns using a step response to create grayscale imagesbefore comparing one of the plurality of dynamic reference images to thecorresponding one of the plurality of images for each of the pluralityof customized patterns to detect defects in the plurality of unitspecific patterns.

The method can further comprise providing a plurality of CAD imagescomprising a CAD image corresponding to each of the unit specificpatterns formed over each of the plurality of semiconductor die, whereinthe plurality of unique reference standards comprise geometry extractedfrom the plurality of CAD images to create extracted CAD geometry in acommon space, wherein the plurality of images for each of the pluralityof unit specific patterns comprise geometry extracted from the pluralityof images to create extracted image geometry in the common space, andwherein detecting defects in the plurality of unit specific patternscomprises detecting defects in the plurality of unit specific patternsby comparing extracted CAD geometry and the extracted image geometry inthe common space.

The method can further comprise providing a plurality of computer-aideddesign (CAD) images comprising a CAD image corresponding to each of theunit specific patterns formed over each of the plurality ofsemiconductor die, converting the plurality of images of the unitspecific patterns from grayscale images to binary images to form aplurality of binary images for the plurality of unit specific patterns,and detecting defects in the plurality of unit specific patterns bycomparing binary data from the plurality of CAD images and the pluralityof binary images for the plurality of unit specific patterns.

The method can further comprise forming the plurality of unit specificpatterns comprising one or more redistribution layers (RDLs), traces,vias, pillars, columns, under bump metallizations (UBMs), or bumps. Themethod can further comprise determining which of the plurality of uniquesemiconductor packages are known good units from detecting defects inthe plurality of unit specific patterns.

In another aspect, a method of AOI for a plurality of uniquesemiconductor packages can comprise acquiring a plurality of images byacquiring an image for each of a plurality of unit specific patternsformed on a reconstituted wafer, creating a plurality of uniquereference standards by creating a unique reference standard for each ofthe plurality of unit specific patterns, and detecting defects in theplurality of unit specific patterns by comparing one of the plurality ofunique reference standards to a corresponding one of the plurality ofimages for each of the plurality of unit specific patterns.

The method of AOI for a plurality of unique semiconductor packages canfurther comprise pre-processing the plurality of images for each of theplurality of unit specific patterns by converting the plurality ofimages into a plurality of binary images, the plurality of binary imagesindicating conductive paths and non-conductive paths, creating theplurality of unique reference standards as a plurality of net lists ofXY coordinates, and comparing one of the plurality of net lists of XYcoordinates to the corresponding one of the plurality of binary imagesfor each of the plurality of unit specific patterns by mapping the oneof the plurality of net lists of the XY coordinates onto the one of theplurality of binary images for each of the plurality of unit specificpatterns. The method can further comprise finding a path between XYcoordinates of one of the plurality of net lists within the conductivepaths of the binary images using a search algorithm or connectivityalgorithm to validate electrical connectivity. The method can furthercomprise verifying that separate nets of the plurality of net lists arenot connected using a pixel expansion algorithm or fill algorithm.

The method of AOI for a plurality of unique semiconductor packages canfurther comprise providing a plurality of computer-aided design (CAD)images comprising a CAD image corresponding to each of the unit specificpatterns formed over each of the plurality of semiconductor die, andcreating the plurality of unique reference standards by creating aplurality of dynamic reference images by rasterizing or modeling theplurality of CAD images for each of the plurality of unit specificpatterns. The method can further comprise rasterizing the plurality ofCAD images for each of the plurality of unit specific patterns using astep response to create grayscale images before comparing one of theplurality of dynamic reference images to the corresponding one of theplurality of images for each of the plurality of customized patterns todetect defects in the plurality of unit specific patterns.

The method can further comprise providing a plurality of CAD imagescomprising a CAD image corresponding to each of the unit specificpatterns formed over each of the plurality of semiconductor die, whereinthe plurality of unique reference standards comprise geometry extractedfrom the plurality of CAD images to create extracted CAD geometry in acommon space, wherein the plurality of images for each of the pluralityof unit specific patterns comprise geometry extracted from the pluralityof images to create extracted image geometry in the common space, andwherein detecting defects in the plurality of unit specific patternscomprises detecting defects in the plurality of unit specific patternsby comparing extracted CAD geometry and the extracted image geometry inthe common space.

The method of AOI for a plurality of unique semiconductor packages canfurther comprise providing a plurality of CAD images comprising a CADimage corresponding to each of the unit specific patterns formed overeach of the plurality of semiconductor die, converting the plurality ofimages of the unit specific patterns from grayscale images to binaryimages to form a plurality of binary images for the plurality of unitspecific patterns, and detecting defects in the plurality of unitspecific patterns by comparing binary data from the plurality of CADimages and the plurality of binary images for the plurality of unitspecific patterns.

The method of AOI for a plurality of unique semiconductor packages canfurther comprise forming the plurality of unit specific patternscomprising one or more RDLs, traces, vias, pillars, columns, UBMs, orbumps. The method can further comprise determining which of theplurality of unique semiconductor packages are known good units fromdetecting defects in the plurality of unit specific patterns.

The foregoing and other aspects, features, and advantages will beapparent to those artisans of ordinary skill in the art from theDESCRIPTION and DRAWINGS, and from the CLAIMS.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C illustrate a plurality of semiconductor die for use in asemiconductor package or embedded die package in accordance with anembodiment of the disclosure.

FIGS. 2A and 2B illustrate various views of a semiconductor package.

FIG. 3 illustrates a flowchart of a method of AOI for unit specificpatterning.

FIG. 4 illustrates a flowchart of an image undergoing image processing.

FIGS. 5A-5F illustrate a plurality of plan views of a portion of asemiconductor device used in a method of AOI.

FIG. 6 illustrates a flowchart of a method of AOI for unit specificpatterning.

FIGS. 7A-7D illustrate a plurality of plan views of a portion of asemiconductor device used in a method of AOI.

FIGS. 8A and 8B illustrate flowcharts of a method of AOI for unitspecific patterning.

FIGS. 9A-9D illustrate a plurality of plan views of a portion of asemiconductor device used in a method of AOI.

FIG. 10 illustrates a flowchart of a method of AOI for unit specificpatterning.

FIGS. 11A-11C illustrate a plurality of plan views of a portion of asemiconductor device used in a method of AOI

DETAILED DESCRIPTION

The present disclosure includes one or more embodiments in the followingdescription with reference to the figures, in which like numeralsrepresent the same or similar elements. It will be appreciated by thoseskilled in the art that the description is intended to coveralternatives, modifications, and equivalents as may be included withinthe spirit and scope of the disclosure as defined by the appended claimsand their equivalents as supported by the following disclosure anddrawings.

In the following description, numerous specific details are set forth,such as specific configurations, compositions, and processes, etc., inorder to provide a thorough understanding of the disclosure. In otherinstances, well-known processes and manufacturing techniques have notbeen described in particular detail in order to not unnecessarilyobscure the disclosure. Furthermore, the various embodiments shown inthe FIGs. are illustrative representations and are not necessarily drawnto scale.

The word “exemplary,” “example” or various forms thereof are used hereinto mean serving as an example, instance, or illustration. Any aspect ordesign described herein as “exemplary” or as an “example” is notnecessarily to be construed as preferred or advantageous over otheraspects or designs. Furthermore, examples are provided solely forpurposes of clarity and understanding and are not meant to limit orrestrict the disclosed subject matter or relevant portions of thisdisclosure in any manner. It is to be appreciated that a myriad ofadditional or alternate examples of varying scope could have beenpresented, but have been omitted for purposes of brevity.

The terms “over,” “between,” and “on” as used herein refer to a relativeposition of one layer with respect to other layers. One layer depositedor disposed above or under another layer may be directly in contact withthe other layer or may have one or more intervening layers. One layerdeposited or disposed between layers may be directly in contact with thelayers or may have one or more intervening layers. In contrast, a firstlayer “on” a second layer is in contact with that second layer.

Semiconductor devices are generally manufactured using two complexmanufacturing processes: front-end manufacturing and back-endmanufacturing. Front-end manufacturing involves the formation of aplurality of die on the surface of a semiconductor wafer. Each die onthe wafer contains active and passive electrical components, which areelectrically connected to form functional electrical circuits. Activeelectrical components, such as transistors and diodes, have the abilityto control the flow of electrical current. Passive electricalcomponents, such as capacitors, inductors, resistors, and transformers,create a relationship between voltage and current necessary to performelectrical circuit functions.

Passive and active components are formed over the surface of thesemiconductor wafer by a series of process steps including doping,deposition, photolithography, etching, and planarization. Dopingintroduces impurities into the semiconductor material by techniques suchas ion implantation or thermal diffusion. The doping process modifiesthe electrical conductivity of semiconductor material in active devices,transforming the semiconductor material into an insulator, conductor, ordynamically changing the semiconductor material conductivity in responseto an electric field or base current. Transistors contain regions ofvarying types and degrees of doping arranged as necessary to enable thetransistor to promote or restrict the flow of electrical current uponthe application of the electric field or base current.

Active and passive components are formed by layers of materials withdifferent electrical properties. The layers can be formed by a varietyof deposition techniques determined in part by the type of materialbeing deposited. For example, thin film deposition can involve chemicalvapor deposition (CVD), physical vapor deposition (PVD), electrolyticplating, and electroless plating processes. Each layer is generallypatterned to form portions of active components, passive components, orelectrical connections between components.

The layers can be patterned using photolithography. Patterning is thebasic operation by which portions of the top layers on the semiconductorwafer surface are removed. Portions of the semiconductor wafer can beremoved using photolithography, photomasking, masking, oxide or metalremoval, photography and stenciling, and microlithography.Photolithography includes forming a pattern in reticles or a photomaskand transferring the pattern into the layer to be patterned such assurface layers of the semiconductor wafer. Photolithography forms thehorizontal dimensions of active and passive components on the surface ofthe semiconductor wafer in a two-step process. First, the pattern on thereticle or masks is transferred into a layer of photoresist. Photoresistis a light-sensitive material that undergoes changes in structure andproperties when exposed to light. The process of changing the structureand properties of the photoresist occurs as either negative-actingphotoresist or positive-acting photoresist. Second, the photoresistlayer is transferred into the wafer surface. The transfer occurs whenetching removes the portion of the top layers of semiconductor wafer notcovered by the photoresist. Alternatively, some types of materials arepatterned by directly depositing material into the areas or voids formedby the photoresist or by a previous deposition/etch process usingtechniques such as electroless and electrolytic plating. The chemistryof photoresists is such that the photoresist remains substantiallyintact and resists removal by chemical etching solutions or platingchemistries while the portion of the top layers of the semiconductorwafer not covered by the photoresist is removed or is added to byplating. The process of forming, exposing, and removing the photoresist,as well as the process of removing a portion of the semiconductor waferor adding to a portion of the wafer can be modified according to theparticular resist used and the desired results.

In negative-acting photoresists, photoresist is exposed to light and ischanged from a soluble condition to an insoluble condition in a processknown as polymerization. In polymerization, unpolymerized material isexposed to a light or energy source and polymers form a cross-linkedmaterial that is etch-resistant. In most negative resists, the polymersare polyisopremes. Removing the soluble portions (i.e. the portions notexposed to light) with chemical solvents or developers leaves a hole inthe resist layer that corresponds to the opaque pattern on the reticle.A mask whose pattern exists in the opaque regions is called aclear-field mask.

In positive-acting photoresists, photoresist is exposed to light and ischanged from a relatively nonsoluble condition to a much more solublecondition in a process known as photosolubilization. Inphotosolubilization, the relatively insoluble resist is exposed to theproper light energy and is converted to a more soluble state. Thephotosolubilized part of the resist can be removed by a solvent in thedevelopment process. The basic positive photoresist polymer is thephenol-formaldehyde polymer, also called the phenol-formaldehyde novolakresin. Removing the soluble portions (i.e. the portions exposed tolight) with chemical solvents or developers leaves a hole in the resistlayer that corresponds to the transparent pattern on the reticle. A maskwhose pattern exists in the transparent regions is called a dark-fieldmask. After removal of the top portion of the semiconductor wafer notcovered by the photoresist, the remainder of the photoresist is removed,leaving behind a patterned layer.

Alternatively, photolithography can be accomplished without the use of aphotoresist when the material to be patterned is itself photosensitive.In this case, the photosensitive material is coated on the devicesurface using spin coating, lamination, or other suitable depositiontechnique. A pattern is then transferred from a photomask to thephotosensitive material using light in an operation typically calledexposure. In an embodiment, the portion of the photosensitive materialsubjected to light is removed, or developed, using a solvent, exposingportions of the underlying layer. Alternatively, in another embodiment,the portion of the photosensitive material not subjected to light isremoved, or developed, using a solvent, exposing portions of theunderlying layer. The remaining portions of the photosensitive film canbecome a permanent part of the device structure.

Depositing a thin film of material over an existing pattern canexaggerate the underlying pattern and create a non-uniformly flatsurface. A uniformly flat surface is required to produce smaller andmore densely packed active and passive components. Planarization can beused to remove material from the surface of the wafer and produce auniformly flat surface. Planarization involves polishing the surface ofthe wafer with a polishing pad. An abrasive material and corrosivechemical are added to the surface of the wafer during polishing.Alternatively, mechanical abrasion without the use of corrosivechemicals is used for planarization. In some embodiments, purelymechanical abrasion is achieved by using a belt grinding machine, astandard wafer backgrinder, surface lapping machine, or other similarmachine. The combined mechanical action of the abrasive and corrosiveaction of the chemical removes any irregular topography, resulting in auniformly flat surface.

Back-end manufacturing refers to cutting or singulating the finishedwafer into the individual semiconductor die and then packaging thesemiconductor die for structural support and environmental isolation. Tosingulate the semiconductor die, the wafer can be cut alongnon-functional regions of the wafer called saw streets or scribes. Thewafer is singulated using a laser cutting tool or saw blade. Aftersingulation, the individual semiconductor die are mounted to a packagesubstrate that includes pins or contact pads for interconnection withother system components. Contact pads formed over the semiconductor dieare then connected to contact pads within the package. The electricalconnections can be made with solder bumps, stud bumps, conductive paste,redistribution layers, or wirebonds. An encapsulant or other moldingmaterial is deposited over the package to provide physical support andelectrical isolation. The finished package is then inserted into anelectrical system and the functionality of the semiconductor device ismade available to the other system components.

The electrical system can be a stand-alone system that uses thesemiconductor device to perform one or more electrical functions.Alternatively, the electrical system can be a subcomponent of a largersystem. For example, the electrical system can be part of a cellularphone, personal digital assistant (PDA), digital video camera (DVC), orother electronic communication device. Alternatively, the electricalsystem can be a graphics card, network interface card, or other signalprocessing card that can be inserted into a computer. The semiconductorpackage can include microprocessors, memories, application specificintegrated circuits (ASIC), logic circuits, analog circuits, RFcircuits, discrete devices, or other semiconductor die or electricalcomponents. Miniaturization and weight reduction are essential for theproducts to be accepted by the market. The distance betweensemiconductor devices must be decreased to achieve higher density.

By combining one or more semiconductor packages over a single substrate,manufacturers can incorporate pre-made components into electronicdevices and systems. Because the semiconductor packages includesophisticated functionality, electronic devices can be manufacturedusing less expensive components and a streamlined manufacturing process.The resulting devices are less likely to fail and less expensive tomanufacture resulting in a lower cost for consumers.

In the following discussion, certain embodiments are described withregard to the formation of a single die FOWLP, though embodiments of thedisclosure are not limited to such. Embodiments of the disclosure may beused in any panelized packaging application including single-dieapplications, multi-die modules, die embedded in a printed wiring boardpanel or PCB, some combination of a die(s) and a passive component(s)within a module, or some combination of one or more device unit(s) andanother component(s) within a module.

FIG. 1A shows a plan view of a semiconductor wafer 20 with a basesubstrate material 22, such as, without limitation, silicon, germanium,gallium arsenide, indium phosphide, or silicon carbide, for structuralsupport. A plurality of semiconductor die or components 24 is formed onwafer 20 separated by a non-active, inter-die wafer area or saw street26 as described above. Saw street 26 provides cutting areas to singulatesemiconductor wafer 20 into individual semiconductor die 24.

FIG. 1B shows a cross-sectional view of a portion of semiconductor wafer20 shown previously in the plan view of FIG. 1A. Each semiconductor die24 has a backside or back surface 28 and active surface 30 opposite thebackside. Active surface 30 contains analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed within the die and electrically interconnectedaccording to the electrical design and function of the semiconductordie. For example, the circuit may include one or more transistors,diodes, and other circuit elements formed within active surface 30 toimplement analog circuits or digital circuits, such as DSP, ASIC,memory, or other signal processing circuit. Semiconductor die 24 mayalso contain integrated passive devices (IPDs), such as inductors,capacitors, and resistors, for RF signal processing.

An electrically conductive layer 32 is formed over active surface 30using PVD, CVD, electrolytic plating, electroless plating process, orother suitable metal deposition process. Conductive layer 32 can be oneor more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni),gold (Au), silver (Ag), or other suitable electrically conductivematerial. Conductive layer 32 operates as contact pads or bond padselectrically connected to the circuits on active surface 30. Conductivelayer 32 can be formed as contact pads disposed side-by-side a firstdistance from the edge of semiconductor die 24, as shown in FIG. 1B.Alternatively, conductive layer 32 can be formed as contact pads thatare offset in multiple rows such that a first row of contact pads isdisposed a first distance from the edge of the die, and a second row ofcontact pads alternating with the first row is disposed a seconddistance from the edge of the die. In another embodiment, conductivelayer 32 can be formed as contact pads disposed in an array across anentire surface area of semiconductor die 24. The full array of contactpads can be formed in a regular or irregular pattern across the entiresurface of semiconductor die 24 according to the configuration anddesign of the semiconductor die. Similarly, a size, shape, ororientation of the contact pads can also be irregular with respect toeach other and can include a length of conductive material that routessignals laterally across active surface 30 of semiconductor die 24.

In FIG. 1C, semiconductor wafer 20 undergoes an optional grindingoperation with grinder 34 to planarize the surface and reduce thicknessof the semiconductor wafer. A chemical etch can also be used to removeand planarize semiconductor wafer 20. Semiconductor wafer 20 issingulated through saw street 26 using a saw blade or laser cutting tool35 into individual semiconductor die 24.

FIGS. 2A and 2B show a plurality of semiconductor packages orsemiconductor devices 50 formed and inspected using a method of AOI forfeatures formed with unit specific pattering, package specificpatterning, customized patterning, or unique patterning, which is alsoknown under the trademark Adaptive Patterning™. Unit specific patterningrefers to a design method that adapts circuitry, portions of a build-upstructure, such as interconnect structures, build-up interconnectstructures, one or more RDLs, traces, patterned conductive layers,routing, vias, pillars, columns, and UBMs, (referred to collectively as“circuitry”) to align with the die placement misalignment or othermisalignment in the X, Y, and Theta directions. The unit specificpattering can comprise one or more patterning techniques to control forplacement misalignment in the X, Y, and Theta directions, including: (i)unit specific routing, which is also known under the trademark AdaptiveRouting™, and (ii) unit specific patterning, which is also known underthe trademark Adaptive Patterning™.

Unit specific patterning refers to a design method that adapts circuitryto align with the die placement misalignment or other misalignment inthe X, Y, and Theta directions by utilizing an auto-routing algorithm tocomplete the circuitry of the semiconductor package in which thecircuitry is being formed. In some instances, the unit specificpatterning can be formed or patterned together with a pre-stratum unitdesign. The prestratum a unit design can comprise fixed circuitry orrouting that can be partially routed from the ball grid array (BGA) padstowards contact pads 32 or copper (Cu) pillar pads over thesemiconductor die 24 for a semiconductor package, such as a fully-moldedsemiconductor package. The remaining portion of the package circuitry orrouting that is not fixed, which can include about 5-10% of the routing,can be customized or dynamic, and can be completed by an autorouter thatcreates routing or other structure adapted to the die orientationmisalignment in X, Y, and Theta.

Unit specific alignment refers to a design method that adapts circuitryor portions of a build-up structure to align with the die placementmisalignment or other misalignment in the X, Y, and Theta directions byrotating, translating in XY directions, or both, features of apre-defined unit.

FIG. 2A shows a plurality of unique semiconductor packages orsemiconductor device 50 being singulated by using the saw blade or lasercutting tool 35 from a reconstituted wafer or molded panel 52. Thesemiconductor packages 50 can comprise fan-in or fan-out WLCSPs that canbe fully molded or encapsulated within encapsulant or mold compound 54in either a die up or die down position. As used herein, die up refersto a semiconductor die comprising an active surface and a back surfaceopposite the active surface that is positioned such that the backsurface is coupled to, and oriented towards, a carrier or substrate(hereinafter carrier) and the active surface of the semiconductor die isoriented away from the carrier when the semiconductor die is mounted tothe carrier. As used herein, die down refers to a semiconductor diecomprising an active surface and a back surface opposite the activesurface that is positioned such that the active surface is coupled to,and oriented towards, the carrier and the back surface of thesemiconductor die is oriented away from the carrier when thesemiconductor die is mounted to the carrier.

Semiconductor packages 50 can comprise a first via or opening 56 thatcan be formed in a first layer, such as a polymer layer, insulatinglayer, or first polymer layer 58 deposited on a native semiconductorwafer 20 comprising semiconductor die 24. Vias 56 can be opened directlyon the die pads 32 and saw street removal regions 26 can be defined forthe fab saw street region(s).

A pillar, copper pillar, post, or conductive interconnect 60 can be madeof any suitable metal or conductive material and formed after theformation of via 56, after formation of a RDL 62 on the native wafer 20,or both. RDL, routing, or interconnect 62 can be formed as a fan-in or afan-out RDL. The pillars 60 can be formed by plating or other suitableprocess to a defined thickness, such as about 5-50 or 5-30 micrometers(μm) before singulation of the native wafer 20. After formation of thecopper pillars 60, the semiconductor die 24 can be embedded or moldedwithin encapsulant 54 to form the reconstituted wafer or molded panel52. The reconstituted wafer or molded panel 52 can be of any size ofshape, and can include a wafer, fan-out wafer or panel, embedded diepanel, substrate or derivatives thereof. Additionally, the reconstitutedwafer 52 may be formed using a PCB process wherein the semiconductor die24 is embedded within a multi-layer PCB substrate or board. RDL 62 canbe a conductive layer that is deposited on the native wafer 20, in thevia 56, and on polymer layer 58 to connect the die pad 32 to the pillars60 at locations within a footprint of semiconductor die 24. The routing62 can be created by a combination of metal deposition, photo, and etchprocesses.

A second via, panel via, or opening 66 can be formed in a polymer layer,insulating layer, or second polymer layer 64 deposited over thereconstituted wafer 52, the semiconductor die 24, and on encapsulant 54and on an exposed end of pillar 60. Vias 66 can be opened directly onthe pillars 60 and extend completely through the polymer layer 64. Insome instances the vias 66 can also extend through some of encapsulant54 before arriving at the pillars 60 so that a layer of encapsulant 54can be present between some but not all of the end of pillar 60 and thepolymer layer 64 in which the vias 66 are formed. The vias 66 can beformed using a unit-specific process or by unit specific patterning toaccount for die shift or shifting of semiconductor die 24 when thereconstituted wafer 52 is formed by disposing the encapsulant 54 aroundthe semiconductor die 24.

One or more RDL, panel RDL, routing, or interconnect layers 68 can beformed as a fan-in or a fan-out RDL. RDL 68 can be a conductive layerthat is deposited over the reconstituted wafer 52, in the via 66, and onpolymer layer 64 to connect or contact the pillars 60 at locations bothwithin and without a footprint of semiconductor die 24. The RDL 68 canbe created by a combination of metal deposition, photo, and etchprocesses using a unit-specific process or by unit specific patterningto account for die shift or shifting of semiconductor die 24 and aposition of vias 66. In some instances the vias 66 can be filled with aconductive interconnect, pillar, post, or conductive via that isseparate from the RDL 68 so that the RDL does not extend down into thevia 66. The vias 66, including a position or location of the vias 66 canbe defined to allow for connectivity from locations of the pillars theRDL 68. Saw street removal regions for the reconstituted panel 52 can bedefined for the semiconductor package 50 saw street regions by or nearthe locations of the RDLs 68. As such, the RDL 68 can comprise pads orball grid array (BGA) pads 70 that form part of a connection between thepillars 60 and the BGA pads 70.

A third via, under bump via, or opening 72 can be formed in a polymerlayer, insulating layer, or third polymer layer 74 deposited over thepolymer layer 64, RDL 68, and BGA pads 70. Polymer layer 74 can be thesecond polymer layer formed on the reconstituted wafer 52 when just oneRDL 68 is present. Alternatively, when additional layers of routing aredesirable, then additional polymer or insulating layers can also bepresent. In any case, the vias 72 can be defined in such a way so as toprovide or allow for connectivity between the RDL 68 and thesubsequently formed under bump metallization/metallurgy (UBM) layer orunder bump via (UBV) 76. The UBM can be a multiple metal stack with oneor more of an adhesion layer, barrier layer, seed or wetting layer. Thepositions or locations of the UBMs 76 can define the locations of thebumps or package interconnects 78, which determine the BGA locations andthe final package interconnect locations which can be held constant withrespect to a package outline and be independent of misalignment ofsemiconductor die 24 within the package due to the unit specificpatterning. Taken together, the unit specific patterning can be used information of the build-up interconnect layer or build-up interconnectlayers 80, which can include features 58-78 or 64-78.

Semiconductor packages 50 can also comprise and optional backsidecoating or die attach material 82. Backside coating 82 can extend overan entire backside of the package 50, or can be limited within afootprint of the semiconductor die.

FIG. 2B shows a plan view of a bottom side of the semiconductor package50, which was shown in cross-sectional view in FIG. 2A. FIG. 2B showsthe semiconductor package 50 with a package outline 90 and asemiconductor die outline 92 for semiconductor die 24. Package 50 showspads 70 and traces 71 of RDL 68. A UBM mask can be formed over thepackage 50 with openings over the pads 70. The package 50 includes unitspecific regions, adaptive regions, or bounding boxes 94 in which unitspecific patterning can occur, such as when a prestratum is used. Inother instances, unit specific patterning can occur without respect to acontained unit specific region 94, or stated another way, the unitspecific region 94 can include an entire surface of footprint of thepackage 50. The package 50 can also include fiducials, L-fiducials, oralignment fiducials 96.

Continuing from FIGS. 2A and 2B, a system and method for AOI of packagesformed with unit specific patterning for defects, is discussed ingreater detail. The unit specific patterning of packages 50 can comprisea system and method for adjusting elements of a semiconductor package,including one or more parts, elements, or features of build-upinterconnect structures 80. Unit specific patterning can compensate forshift or relative movement of semiconductor die within a panelizedpackage or reconstituted wafer that can occur, for example, duringencapsulation of semiconductor die. The relative position or shift ofthe semiconductor die can be with respect to the final package, withrespect to a position or location on a panel or reconstituted wafer, orboth. The AOI system and method for unit specific patterning disclosedherein allows for inspecting unit specific patterned packages 50 whilepart of the reconstituted wafer 52, whether the package 50 is partiallyor totally completed. However, before continuing to describe AOI forpackages 50 with respect to FIG. 3, a number of Applicant's insightsinto the benefits of AOI for packages comprising unit specificpatterning are presented.

Conventional optical inspection uses a golden image based methodology,as described in the background section. However, conventional opticalinspection is unable to inspect packages and structures for packagesthat including unit specific patterning. Conventional optical inspectionis ineffective for unit specific patterning because the features orpatterns inspected during optical inspection may, when correctly formedaccording to the desired unit specific design, be unique and not conformto an average or golden image. To the contrary, a unit specific patterncould have been incorrectly or improperly executed or built if anentirety of the unit specific pattern conformed to an entirety of anaverage or golden image. As such, for applications involving unitspecific patterning, a golden image cannot be created from known-goodparts for an entirety of the pattern since portions of the patternedmaterial can be different or vary from an “average” when correctlyconstructed.

Thus, current optical inspection methods can be used to inspect onlylimited portions of a unit specific patterned package, and not anentirety of the package. For unit specific designs wherein dynamictraces are drawn from a fixed pattern or prestratum to shifting viacapture pads or traces 71, the unit specific region or bounding box 94around each dynamic trace formed within the unit specific region 94 canbe ignored and the stationary or fixed portion of the pattern, i.e. theprestratum, can be inspected. However, this method of partial inspectiondoes not inspect the unit specific, adaptive, custom, or dynamicallyformed traces for defects.

For unit specific designs where the geometry of the redistribution layeris fixed, but is translated and rotated to match die shift, a goldenimage can be re-aligned to the shifted RDL pattern before performing thecomparison. However, all layers under inspection may not have the samealignment. Therefore this method requires inspecting each set of alignedlayers separately, or ignoring regions of misalignment. As indicatedabove, unit specific alignment wafers with only the RDL layer, such asRDL 68, being customized as part of a unit-specific design can beanalyzed with a traditional golden image method by aligning the goldenimage to the acquired image. However, as additional features are addedin subsequent steps, such as UBM layer 76 or bumps 78, the additionalfeatures will not necessarily be aligned to the RDL patterns, and theacquired image will be made from two shifted or rotated layers. As everysemiconductor die 24 could have a different shift or rotation, thetraditional golden image method is problematic, time consuming,expensive, and technically unsuited for use in performing a completeoptical inspection.

Thus, a need exists for AOI of unit specific patterning that allows forefficient and reliable inspection for unit specific patterning inpackages 50 and detection of defects. A defect can be defined as thedeviation from the perfect product or golden image. The system andmethod for AOI of packages 50 comprising unit specific patterningaccounts for the dynamic patterns created with unit specific patterningby changing the definition of a perfect product for every die. Theperfect product itself can be a dynamic, unique, or unit specificreference or standard, such as unique reference standard, against whichthe unit specific pattern or features of the build-up interconnect layer80 can be measured, compared, or tested. As such the unique referencestandards are adjusted for, include, or take account of, elements of thepatterns, features, or unit specific patterns on each package tocompensate for unit specific patterning.

Additional consideration is now given to how AOI for uniquesemiconductor packages comprising unit specific patterning within a samereconstituted wafer can be performed. The unique reference standardscreated for each package, once created, can then be compared to imagescaptured during inspection of unit specific patterns formed over orconnected to the semiconductor die. As will be discussed with respect tothe following FIGs., the unique reference standards can be an imagescreated from the CAD artwork for each package. Pre-processing may beperformed on the reference images and the images of the inspected partbefore comparison. Alternatively, and also as discussed with respect tothe following FIGs., the reference can be a geometry dataset describingthe expected features.

One way of providing AOI for a plurality of unique semiconductorpackages comprising unit specific patterning includes using computeraided design (CAD) files. The solutions described below involvecomparing the design or CAD files to one or more images of the unitspecific patterns acquired from an AOI system. Of note is that the CADfiles are binary, while the acquired images from the AOI are gray scale.Thus, to compare, by subtraction or other method, the CAD files and theacquired images, a number of approaches can be used. In a first aspect,binary CAD files can be converted to gray scale as part or formingunique reference standards, such as through acquired image space, toallow a comparison between a unique reference standard and acorresponding unit specific pattern. The first aspect is presented ingreater detail with respect to FIGS. 3-5F. In a second aspect, acomparison can be conducted by converting both the CAD files and theacquired image to a common space or third space. The second aspect ispresented in greater detail with respect to FIGS. 6-7D. In a thirdaspect, gray scale images acquired by visual inspection can be convertedto a binary format such as, or compatible with, CAD data space. Thethird aspect is presented in greater detail with respect to FIGS. 8A-9D.In implementing the various aspects of the method of AOI for a pluralityof unique semiconductor packages, multiple CAD files can be needed tomake a complete product. Furthermore, the various aspects can be usedtogether with each other and with additional aspects not relying on CADfiles.

FIG. 3 shows a flow chart or method 100 that presents informationrelative to converting CAD data into acquired image space. CAD data or aCAD design 108 can be in the form of one or more CAD files that caninclude one or more layers, such as CAD file Layer 1 or CAD file 102,CAD file Layer 2 or CAD file 104, and CAD file Layer 3 or CAD file 106.All the CAD files 102, 104, and 106, as well as an acquired image 110 ofone or more unit specific patterns can be given as inputs to a model112, which creates a dynamic reference image, unique reference standard,or unique reference image 114. The unique reference standard 114 can becreated for every acquired image 110 and the unique reference standard114 and a corresponding or respective acquired image 110 can then becompared to detect, determine, or identify defects. A comparison of aunique reference standard 114 and an acquired image 110 can be made forevery semiconductor die 24 or one or more corresponding features ofbuild-up interconnect 80 for each semiconductor die 24 included withinthe reconstituted wafer 52.

As such, the unique reference standard 114 can operate in place of, oras an improved or unique, “golden image,” the unique reference standard114 being a unique idealized image for each semiconductor package 50 orbuild-up structure 80. In applying defect detection algorithm 116, ifthe deviations derived from comparing of each pixel of an acquired image110 and a corresponding unique reference standard 114 are within aspecified gray scale range, then the part, feature, or element ofbuild-up interconnect 80 captured in the acquired image 110 can beclassified as defect-free. Two example models 112 used to generate thegray scale dynamic reference images include: 1) rasterizing the CADfiles 102, 104, and 106, or convert an image stored as an outline withinthe files 102, 104, 106 into pixels that can be displayed on a screen orprinted; and 2) modeling the relationship between the acquired image andits CAD files.

In some instance, the unique reference standard 114 can be generated byrasterizing the CAD files 102, 104, and 106, and then filling therasterized image with specific pixel values corresponding to thecombinations of materials on the part. This is discussed in greaterdetail with respect to FIG. 4, and creates unique reference standard 114that will be used for subtractive comparison.

In other instances, the unique reference standard 114 can also begenerated by modeling the relationship between the acquired image 110and the CAD files 102, 104, and 106 within model 112. The edge responseof material on the inspected part, such as a unit specific pattern, canbe used to characterize a relationship between the design files the CADfiles 102, 104, and 106 and the image 110 to generate unique referencestandard 114. Model 112 can include use one or more of an edge responsefunction, a line spread function (LSF), which is the derivative of theedge response function, or a point spread function (PSF). A PSF can becalculated from the LSF. Assuming that the system is linear and shiftinvariant within the model 112, the PSF can be used to produce theunique reference standard 114 for any CAD input file, such as CAD files102, 104, and 106.

For both rasterizing and modeling methods within model 112, the uniquereference standard 114 can be further processed before comparison atdefect detection algorithm 116 to better model noise or other variationsthat are present in the captured images 110 of inspected parts. FIG. 4provides an example of how reference images from the CAD files 102, 104,and 106 can undergo image processing at model 112 using a step responseto create a better or more accurate unique reference standard 114.

FIG. 4 shows a flow chart 120 of how the image from the CAD files 102,104, and 106 is processed to make it look more like the image 110. Thedata in CAD files 102, 104, and 106 is binary, either something is drawnor not drawn, while the images 110 have variations in topography,material thickness, and slope. The variations in a reference image 124,such as a conventional golden image or the acquired image 110, can becaptured by the AOI or inspection device by measuring how the referenceimage 124 changes when transitioning from no patterned feature present(like no RDL 62) to a patterned feature being present (like RDL 62). Thestep between no feature present to a feature being present is referredto as the step response 122, which is illustrated as a line graphshowing increasing intensity aligned with a corresponding bar at thebottom of the graph showing an enlarged gradient of intensity from thestep of no RDL 62 to RDL 62. The step response 122 can then betransformed into an impulse response and convolved with one or more CADbinary images from the CAD files 102, 104, and 106 at model 112. Theoutput from model 112 is the unique reference standard 114 that can havea patterned feature, in this case shown as RDL 62, the patterned featurecomprising a shape of the CAD data, and further including the transitionproperties or step response 122 of the reference image 124. As such, theimages in CAD files 102, 104, and 106 and the captured image 110 aremore statistically similar to image 110 when no defect or error inpatterning is present. Additionally, detecting defects, when defects arepresent, is also made easier when applying defect detection algorithm116.

Measurement of the step response 122 can be done once per wafer, onceper package, or any other number of times until a desired calibration isachieved. Furthermore, more than one step response 122 can be used fordifferent transitions among different patterned features, such asbetween via 56 and RDL 62 or via 66 and RDL 68. Image processing withinmodels like model 112 can be accomplished in a number of ways. Imagescan be converted into CAD image space, or binary space, using thresholdfilters. If both the CAD data and captured data, like data from images110 or 124, are to be used as polygons, the capture image could beprocessed by an edge detection filter.

The images in FIGS. 5A-5E illustrate the process of detecting errors inan acquired image 110 by comparing the image 110 with a CAD design 108.More specifically, FIG. 5A shows a unique reference standard or agenerated reference image 114. FIG. 5B shows an acquired image 110. FIG.5C shows a CAD design 108. FIG. 5D shows a CAD file layer 102, the filelayer being for only the RDL 68. FIG. 5E shows a difference image 117illustrating a subtraction or difference between the acquired image 110and the unique reference standard 114, which can be an output 118. FIG.5F shows defect map 119 that can also be an output 118 that resultsafter processing or running the defect detection algorithm 116.

As such, the method shown and described in FIG. 4 and FIGS. 5A-5F caninclude, first, each layer of the CAD data 108 being rasterized to aseparate image of the same pixel size as the acquired image 110. Next,the unique reference standard or reference image 114 is generated byfilling the regions in the rasterized CAD images with average values foreach material. An overlap of two layers is considered a differentmaterial, since the pixel intensity is different (see example tablebelow). The unique reference standard or reference image 114 an exampleof multiple materials, including overlapping layers. The uniquereference standard or reference image 114 is subtracted pixel-by-pixelfrom the acquired image 110, resulting in the difference image 117 shownin FIG. 5E. Finally, the difference image 117 is threshold filtered, andthen spatially filtered to remove noise. The resulting defect map 119indicates defects with white pixels. Thus, the large blob-shaped defect130 appears as a large white blob in the defect map 119. In addition,missing sections of RDL 68 or traces 71 that are present in the designdata 108, but not the acquired image 110, appear as white traces.

Table 1, included below, shows sample ranges and values for pixel valuesused in the AIO process based on various material types for conversionof CAD images. While each of the material can have a value in a range of0-255, the table shows by material a value that can also be used, or arange including plus or minus 10, 20, 50, or 100 with respect to each ofthe values shown.

TABLE 1 Material Pixel Value (0-255) PRDL 68 PRDL-PVIA1 52 PRDL-PUBV-UBM100 PRDL-UBM 100 Mold 40

FIG. 6 shows a flow chart or method 140 that presents informationrelative to converting CAD data 148 and an acquired image 150 to acommon space. CAD data or a CAD design 158 can be in the form of one ormore CAD files that can include one or more layers, such as CAD fileLayer 1 or CAD file 142, CAD file Layer 2 or CAD file 144, and CAD fileLayer 3 or CAD file 144. All the CAD files 142, 144, and 146, can begiven as inputs to a geometry extractor 152. Similarly, an acquiredimage 150 can be given as an input to a geometry extractor 154. Thegeometry extractor 152 and the geometry extractor 154 can operate usingblob algorithms and edge finding algorithms to process, produce, orboth, polygons, arcs, and circles from the inputs of CAD designs 148 andacquired image 150. For example, the geometry extractor 154 can convertthe acquired image 150 to a set of expected edges, arcs, and circles.Similarly, the the geometry extractor 152 can work with the form ofpolygons, arcs, and circles output from the CAD designs 148, and werenecessary convert the CAD designs 148 to a set of expected edges, arcs,and circles if not output in a desired form. The expected edges, arcs,and circles from the CAD designs 148 and the acquired image 150 can beare morphologically compared to those in the reference, or the uniquereference standard 156. Similarly, the edges, polygons, arcs, andcircles found by the algorithms in the CAD designs 148 and the acquiredimage 150 can be morphologically compared to those in the reference, orunique reference standard 156.

As used herein, the geometry extractor 152 can convert the CAD designs148 to a set of expected edges, arcs, and circles, or to edges and blobsthat operate as a unique reference standard for comparing the uniquereference standard to an image 150 comprising unit specific patterns todetermine defects at defect detection algorithm 156 in the common space.Therefore, the method of AOI of flowchart 140 can comprise detectingdefects in the plurality of unit specific patterns by comparing one ofthe plurality of unique reference standards to a corresponding one ofthe plurality of images for each of the plurality of unit specificpatterns, wherein the plurality of unique reference standards comprisegeometry extracted from the plurality of CAD images to create extractedCAD geometry in a common space, and wherein the plurality of images foreach of the plurality of unit specific patterns comprise geometryextracted from the plurality of images to create extracted imagegeometry in the common space, such that detecting defects in theplurality of unit specific patterns comprises detecting defects in theplurality of unit specific patterns by comparing extracted CAD geometryand the extracted image geometry in the common space.

The images in FIGS. 7A-7D illustrate the process of detecting errors inan acquired image 150 by comparing geometry extracted from CAD data 148and geometry extracted from the image 150 with defect detectionalgorithm 156. More specifically, FIG. 7A shows the acquired image 150.FIG. 7B shows a CAD file layer 142 that includes the UBV layer 76 frompackage 76. FIG. 7C shows edges of the UBV layer 76 and thesemiconductor die outline 92 from the acquired image 150 as produced bythe geometry extractor 154. FIG. 7D shows edges of the UBV layer 76 andthe semiconductor die outline 92 from the CAD file layer 142 as producedby the geometry extractor 152.

An example of the approach or method shown in flowchart 140 can compriseconverting all the features in the acquired image 150 as well as the CADfiles 148 into geometric objects using one or more suitable algorithms,such as, e.g., edge detection algorithms and thresholding algorithms.The examples shown in FIGS. 7A-7D shows using higher intensities atedges of the UBV layer 76 and lower intensity at the dark lines toisolate the features relevant to the UBV layer 76. As shown in theexample, the images can then be broken down to geometrical shapes likecircles and rectangles. The centers and the diameters of the circles, aswell as the position and thickness of the rectangles, can then bechecked against the design values in the CAD files.

FIGS. 8A and 8B show similar flow charts or methods 160 and 180,respectively, that present information relative to converting image datafrom an acquired image to CAD data to allow detection of errors in CADdata space. Flow chart 160 shows an acquired image 162 can include datathat can be processed at “Layer 1 Registration” 166 to include onlyspatial features relevant to a CAD file Layer 1, CAD file, or uniquereference standard 164. The acquired image data within the mask orwithin the footprint 90 of the semiconductor package 50 is expected tobe within a range of gray scale values. Deviations from the gray scalevalues would be classified as error by the defect detection algorithm170. In the absence of error, the defect detection algorithm willproduce an output for layer 1 or output 172. Because images are beingconverted to CAD data space, as many comparisons are needed as thenumber of CAD files. Thus, in the example of FIGS. 8A and 8B, two CADfiles 164, and 184, are being compared and two comparisons are likewiseneeded to produce outputs 172 and 192. Hence the process shown in flow160 in FIG. 8A and in flow 180 in FIG. 8B can be identical orsubstantially identical except for the differences between CAD filelayers, such as CAD file layer 164 and CAD file layer 184. In someinstances, the process flow 160 and the process flow 180 can usedifferent acquired images for acquired image 162 and acquired image 182.In other instances, the process flow 160 and the process flow 180 canuse the same or identical images for both acquired image 162 andacquired image 182. The acquired images 162 and 182 can be identicalbecause a portion of the acquired image being inspected can contain thepatterned portion, feature, or inspected part that corresponds to thepatterned portion, feature, or inspected part included or containedwithin multiple CAD file layers, such as CAD file layer 164 and CAD filelayer 184.

For flow 160, when converting acquired image or image data 162 to CADdata space, the gray-scale image 162 can be converted into a binary file168 to compare against the binary CAD files 164 at the layer 1registration 166. The layer 1 registration 166 can be performed oraccomplished by different algorithms including thresholding, using aspatial mask from the CAD file 164, or a combination of masking andthresholding or other suitable algorithms. The binary image 168 can thenbe subtracted at defect detection algorithm 170 to make a differenceimage 171. Minimum size filters can then applied to the difference image171 to get the defect map 173, which can be produced as output 172.Thus, detection of errors in CAD data space can be achieved, as shown inFIG. 8A, by comparing a unique reference standard 164 and an acquiredimage 162 that has been processed to produce a corresponding image 168,the comparison occurring one layer at a time for every CAD file layer164 for every semiconductor die 24 within the reconstituted wafer 52.

For flow 180, when converting acquired image or image data 182 to CADdata space, the gray-scale image 182 can be converted into a binary file188 to compare against the binary CAD files 184 at the layer 2registration 186. The layer 2 registration 186 can be performed oraccomplished by different algorithms including thresholding, using aspatial mask from the CAD file 184, or a combination of masking andthresholding or other suitable algorithms. The binary image 188 can thenbe subtracted at defect detection algorithm 190 to make a differenceimage 191. Minimum size filters can then applied to the difference image191 to get the defect map 193, which can be produced as output 192.Thus, detection of errors in CAD data space can be achieved, as shown inFIG. 8B, by comparing a unique reference standard 184 and an acquiredimage 182 that has been processed to produce a corresponding image 188,the comparison occurring one layer at a time for every CAD file layer184 for every semiconductor die 24 within the reconstituted wafer 52.

The images in FIGS. 9A-9D illustrate the process of detecting errors inan acquired image 162 by comparing a CAD file or unique referencestandard 164 to image 162 by converting image data from the acquiredimage 162 to corresponding image 168 in CAD data space to allowdetection of errors between the image 162 and the CAD file layer 164.More specifically, FIG. 9A shows an acquired image 162, 182 thatcomprises a unit specific pattern, or patterned feature, formed as anRDL, such as, e.g., RDL 68. FIG. 9B shows a CAD file, 164, 184 thatcomprises a unit specific pattern, or patterned feature, formed as anRDL, such as, e.g., RDL 68. FIG. 9C shows a image 171, 191 between theCAD file layer 164, 184 and binary image 168, 188 that comprises a unitspecific pattern, or patterned feature, formed as an RDL, such as, e.g.,RDL 68. FIG. 9D shows a defect map 173, 193 for defects that exist in aunit specific pattern, or patterned feature, formed as an RDL, such as,e.g., RDL 68.

FIG. 10 presents a flow chart 200 for another method of AOI for aplurality of unique semiconductor packages comprising unit specificpatterning, the method using a net list 202 as a unique referencestandard to compare against a captured image or acquired image 204. Thenet list 202 can specify a plurality of coordinates, such as XYcoordinates or other suitable coordinates used to define a design, area,or net that is associated with, or corresponds to, an electrical net.Examples of such coordinates are shown in FIGS. 11B and 11C as firstcoordinate or XY coordinate 220 and second coordinate or XY coordinate222. Each coordinate in the design can be expected to be conductivelyconnected to all other coordinates on the same net. The net list 202contains a list of coordinates (within a given package 50 or wafer 52)and an associated net for each coordinate. One net list 202 can compriselists of coordinates for a plurality of different electrical nets thatcan be electrically isolated or distinct from each other. The net list202 can be generated by, or created as an output from, an electronic CADtool.

The net list 202 can be checked for electrical connectivity by usingconnectivity algorithm 208. The algorithms used for connectivityalgorithm 208 can be a pixel fill algorithm or a wavefront expansionalgorithm if the check is done on pixel data. If the data is convertedto polygons, the connectivity can be done by checking for polygonoverlap or intersection. When using polygons, the connectivity algorithm208 should ensure that the overlapping polygons when taken together arecontinuous, and not several “islands”. In the event either pixels orpolygons, the data used for the connectivity algorithm 208 can come fromthe acquired image 204, which can undergo pre-processing 206 prior tobeing input to the connectivity algorithm 208. The preprocessing 206 ofthe captured AOI image 204 of the package 50 can undergo pre-processingto transform the acquired image 204 into a binary image of conductivepaths and non-conductive paths that is input to the connectivityalgorithm 208.

For connectivity inspection (which can include identifying both opencircuits and short circuits), the net list 202 can be used as a uniquereference standard when comparing the unique reference standard to theacquired image 204 after pre-processing 206. Thus, the net list 202 canbe used instead of CAD artwork for making the comparison with a uniquereference standard as described with respect to FIGS. 4, 6, and 8.

To verify connectivity of patterned features on the captured AOI image204, the image 204 can be first transformed into a binary image ofconductive paths and non-conductive paths through pre-processing 206.Then coordinates of the net list 202 can be mapped onto the image 204after processing 206, and a search or connectivity algorithm 208 can beused to find a path between the coordinates within the conductiveregions defined by the net list 202. To verify that separate nets withinthe net list 202 are not connected, a pixel expansion algorithm or fillalgorithm can be used to expand around coordinates to fill the region.If the expansion fills all available pixels without the net withouttouching another net, then no short-circuit exists among the nets, andthe information of no short-circuits can be delivered as an output 210.Coordinates of the same net within net list 202 are expected to beelectrically connected by conductive material in the captured images204. During inspection, for each coordinate, an entire shape that isoverlapped, under, or contacted by the coordinate is traced and markedwith an associated net (if not already marked). When the shape under thecoordinate is already marked with a net, the marked net and the currentXY coordinate's net must match or a short will be present. The tracingof the shape under the coordinate can be done with a pixel-wise fillalgorithm. The tracing of the shape under the coordinate can also bedone with an edge detection algorithm to generate a polygon boundary.

Alternative algorithms can be used a part of applying connectivityalgorithm 208 for verifying the connectivity between coordinates orpoints, such as a graph search on the pixel data. When using a graphsearch on the pixel data, one coordinate in the net list is used as thestarting point, and a graph search finds a path through conductivelycolored and contiguous pixels only to the other net list coordinates. Ifsuch a path does not exist, the net has an open. Conversely, to checkfor short-circuits or shorts, the search must also exhaustively verifythat no such path exists to coordinates of other nets. To enhanceperformance, the search can be limited to only nets that are expected toneighbor each other. If the shapes from the captured image are processedinto polygons, the inspection can simply check whether polygons from thesame net overlap and verify that the polygons form a contiguous region.If any of the polygons overlaps a polygon from another net, a shortdefect is present.

As part of the connectivity algorithm 208, spacing between electricalnets from net list 202 can be verified by dilating each polygon or pixelshape before checking for overlaps with other nets. The dilation can beone half of the necessary spacing between nets, or about one half of thenecessary spacing. As used herein, “about” is equal to plus or minus 5%,10%, 20% of the necessary spacing. If the captured image does notcontain shorts after dilation (according to the net list) then thecaptured image does not contain spacing defects. Minimum width can bechecked by eroding each polygon or pixel shape by one half of theminimum feature size, or about one half the feature size. As usedherein, “about” is equal to plus or minus 5%, 10%, 20% of the featuresize. If the connectivity indicated in the net list still exists aftererosion, then the captured image does not contain a minimum widthdefect.

FIGS. 11A-11C show various images relating to the use of the net listmethod 200 for electrical connectivity validation discussed above withrespect to FIG. 10A. FIG. 11A shows an acquired image 204 afterconversion to a binary conductive/non-conductive view by pre-processing206. FIG. 11A also shows tracing and marking of shapes from the acquiredimage 204 by nets, so that a the net list 202 includes a first net 212,a second net 214, a third net 216, and a fourth net 218, where the solidlines enclosing the RDL 68 define the respective nets 212, 214, 216, and218. FIG. 11B shows a first coordinate or XY coordinate 220 within thesecond net 214, with the second net 214 overlapping a shape 224 (shownin gray) of a portion of the acquired image 204. The shape 224 can be ofa portion of a patterned structure or unique patterned structure such asRDL 68. FIG. 11C is similar to FIG. 11B, but shows a second coordinateor XY coordinate 220 from the second net 214 that overlaps the sameshape 224, the shape 224 being marked with the same second net 214,which verifies connectivity of the first coordinate 220 and the secondcoordinate 222. If, however, the shape 224 were marked with differentnets, such as first net 212 and second net 214, the first coordinate 220being within the first net 212 and the second coordinate 222 beingwithin the second net 214, then a short would exist.

A number of different aspects of AOI of uniquely patterned semiconductorpackages 50 have been described. The various aspects could be usedseparately or together for a same package 50, a same reconstituted wafer52, or any other package structure that uses unit specific patterning,such as printed circuit boards or substrates with embedded die or facedown wafer level fan-out packages. The various different aspects ormethods can be better suited for finding different defect types, andsome defect inspections can be done optimally with a combination ofelements from each of the aspects or methods described herein.Additionally, differing aspects or methods of the various AOI methodscould also be used in parallel, or at a same time, to inspect specificregions of a same semiconductor die 24, semiconductor package 50, orreconstituted wafer 52.

In accordance with the foregoing, inspecting a wafer level package usinga dynamic reference and generating the dynamic reference fromper-package CAD artwork provides a novel method for AOI of unit specificpatterning. Accordingly, the AOI method for unit specific patterningfacilitates production of semiconductor packaging comprising unitspecific patterning by allowing for thorough inspection of product forimproved quality control.

Where the above examples, embodiments and implementations referenceexamples, it should be understood by those of ordinary skill in the artthat other manufacturing devices and examples could be intermixed orsubstituted with those provided. In places where the description aboverefers to particular embodiments, it should be readily apparent that anumber of modifications may be made without departing from the spiritthereof and that these embodiments and implementations may be applied toother technologies as well. Accordingly, the disclosed subject matter isintended to embrace all such alterations, modifications and variationsthat fall within the spirit and scope of the disclosure and theknowledge of one of ordinary skill in the art.

What is claimed is:
 1. A method of automated optical inspection (AOI)for a plurality of unique semiconductor packages comprising: providing aplurality of semiconductor die formed as a reconstituted wafer; forminga plurality of unit specific patterns by forming a unit specific patternover each of the plurality of semiconductor die, wherein each of theunit specific patterns is customized to fit its respective semiconductordie; acquiring a plurality of images by acquiring an image for each ofthe plurality of unit specific patterns; creating a plurality of uniquereference standards by creating a unique reference standard for each ofthe plurality of unit specific patterns; detecting defects in theplurality of unit specific patterns by comparing one of the plurality ofunique reference standards to a corresponding one of the plurality ofimages for each of the plurality of unit specific patterns; andsingulating the reconstituted wafer to form the plurality of uniquesemiconductor packages.
 2. The method of AOI of claim 1, furthercomprising: pre-processing the plurality of images for each of theplurality of unit specific patterns by converting the plurality ofimages into a plurality of binary images, the plurality of binary imagesindicating conductive paths and non-conductive paths; creating theplurality of unique reference standards as a plurality of net lists ofXY coordinates; and comparing one of the plurality of net lists of XYcoordinates to the corresponding one of the plurality of binary imagesfor each of the plurality of unit specific patterns by mapping the oneof the plurality of net lists of the XY coordinates onto the one of theplurality of binary images for each of the plurality of unit specificpatterns.
 3. The method of AOI of claim 2, further comprising finding apath between XY coordinates of one of the plurality of net lists withinthe conductive paths of the binary images using a search algorithm orconnectivity algorithm to validate electrical connectivity.
 4. Themethod of AOI of claim 2, further comprising verifying that separatenets of the plurality of net lists are not connected using a pixelexpansion algorithm or fill algorithm.
 5. The method of AOI of claim 1,further comprising: providing a plurality of computer-aided design (CAD)images comprising a CAD image corresponding to each of the unit specificpatterns formed over each of the plurality of semiconductor die; andcreating the plurality of unique reference standards by creating aplurality of dynamic reference images by rasterizing or modeling theplurality of CAD images for each of the plurality of unit specificpatterns.
 6. The method of AOI of claim 5, further comprisingrasterizing the plurality of CAD images for each of the plurality ofunit specific patterns using a step response to create grayscale imagesbefore comparing one of the plurality of dynamic reference images to thecorresponding one of the plurality of images for each of the pluralityof customized patterns to detect defects in the plurality of unitspecific patterns.
 7. The method of AOI of claim 1, further comprising:providing a plurality of computer-aided design (CAD) images comprising aCAD image corresponding to each of the unit specific patterns formedover each of the plurality of semiconductor die; wherein the pluralityof unique reference standards comprise geometry extracted from theplurality of CAD images to create extracted CAD geometry in a commonspace; wherein the plurality of images for each of the plurality of unitspecific patterns comprise geometry extracted from the plurality ofimages to create extracted image geometry in the common space; andwherein detecting defects in the plurality of unit specific patternscomprises detecting defects in the plurality of unit specific patternsby comparing extracted CAD geometry and the extracted image geometry inthe common space.
 8. The method of AOI of claim 1, further comprising:providing a plurality of computer-aided design (CAD) images comprising aCAD image corresponding to each of the unit specific patterns formedover each of the plurality of semiconductor die; converting theplurality of images of the unit specific patterns from grayscale imagesto binary images to form a plurality of binary images for the pluralityof unit specific patterns; and detecting defects in the plurality ofunit specific patterns by comparing binary data from the plurality ofCAD images and the plurality of binary images for the plurality of unitspecific patterns.
 9. The method of AOI of claim 1, further comprisingforming the plurality of unit specific patterns comprising one or moreredistribution layers (RDLs), traces, vias, pillars, columns, under bumpmetallizations (UBMs), or bumps.
 10. The method of AOI of claim 1,further comprising determining which of the plurality of uniquesemiconductor packages are known good units from detecting defects inthe plurality of unit specific patterns.
 11. A method of automatedoptical inspection (AOI) for a plurality of unique semiconductorpackages comprising: acquiring a plurality of images by acquiring animage for each of a plurality of unit specific patterns formed on areconstituted wafer; creating a plurality of unique reference standardsby creating a unique reference standard for each of the plurality ofunit specific patterns; and detecting defects in the plurality of unitspecific patterns by comparing one of the plurality of unique referencestandards to a corresponding one of the plurality of images for each ofthe plurality of unit specific patterns.
 12. The method of AOI of claim11, further comprising: pre-processing the plurality of images for eachof the plurality of unit specific patterns by converting the pluralityof images into a plurality of binary images, the plurality of binaryimages indicating conductive paths and non-conductive paths; creatingthe plurality of unique reference standards as a plurality of net listsof XY coordinates; and comparing one of the plurality of net lists of XYcoordinates to the corresponding one of the plurality of binary imagesfor each of the plurality of unit specific patterns by mapping the oneof the plurality of net lists of the XY coordinates onto the one of theplurality of binary images for each of the plurality of unit specificpatterns.
 13. The method of AOI of claim 12, further comprising findinga path between XY coordinates of one of the plurality of net listswithin the conductive paths of the binary images using a searchalgorithm or connectivity algorithm to validate electrical connectivity.14. The method of AOI of claim 12, further comprising verifying thatseparate nets of the plurality of net lists are not connected using apixel expansion algorithm or fill algorithm.
 15. The method of AOI ofclaim 11, further comprising: providing a plurality of computer-aideddesign (CAD) images comprising a CAD image corresponding to each of theunit specific patterns formed over each of the plurality ofsemiconductor die; and creating the plurality of unique referencestandards by creating a plurality of dynamic reference images byrasterizing or modeling the plurality of CAD images for each of theplurality of unit specific patterns.
 16. The method of AOI of claim 15,further comprising rasterizing the plurality of CAD images for each ofthe plurality of unit specific patterns using a step response to creategrayscale images before comparing one of the plurality of dynamicreference images to the corresponding one of the plurality of images foreach of the plurality of customized patterns to detect defects in theplurality of unit specific patterns.
 17. The method of AOI of claim 11,further comprising: providing a plurality of computer-aided design (CAD)images comprising a CAD image corresponding to each of the unit specificpatterns formed over each of the plurality of semiconductor die; whereinthe plurality of unique reference standards comprise geometry extractedfrom CAD images to create extracted CAD geometry in a common space;wherein the plurality of images for each of the plurality of unitspecific patterns comprise geometry extracted from the plurality ofimages to create extracted image geometry in the common space; andwherein detecting defects in the plurality of unit specific patternscomprises detecting defects in the plurality of unit specific patternsby comparing extracted CAD geometry and the extracted image geometry inthe common space.
 18. The method of AOI of claim 11, further comprising:providing a plurality of computer-aided design (CAD) images comprising aCAD image corresponding to each of the unit specific patterns formedover each of the plurality of semiconductor die; converting theplurality of images of the unit specific patterns from grayscale imagesto binary images to form a plurality of binary images for the pluralityof unit specific patterns; and detecting defects in the plurality ofunit specific patterns by comparing binary data from the plurality ofCAD images and the plurality of binary images for the plurality of unitspecific patterns.
 19. The method of AOI of claim 11, further comprisingforming the plurality of unit specific patterns comprising one or moreredistribution layers (RDLs), traces, vias, pillars, columns, under bumpmetallizations (UBMs), or bumps.
 20. The method of AOI of claim 11,further comprising determining which of the plurality of uniquesemiconductor packages are known good units from detecting defects inthe plurality of unit specific patterns.